PVA brush design advances for Cu/low-k post-CMP cleaning apps
To meet next-generation challenges, polyvinyl alcohol (PVA) brush designs may need further optimization in design and materials, and many of the cleaning chemistries and approaches will have to change ...
32nm node USJ formation using rapid process optimization metrology
Ultra-shallow junctions (USJs) that are <10nm at the 32nm node require the close process optimization of ion implantation (elemental species, energy and dose) with diffusion-less annealing (millise ...
Temporary bonding/debonding for ultrathin substrates
A jointly developed temporary bonding/debonding system designed for ultrathin wafer processing is described, as well as critical parameters to be considered in processing thin wafers, including TSV cr ...
Integrating III-V on silicon for future transistor applications
Since the early 2000s, many new electronic materials have been explored and incorporated into silicon CMOS transistors for enhancing their device performance and energy-efficiency.
High-k goes to production, but arguments continue
The manufacturing infrastructure for high-k stacks is reasonably mature. Manufacturers have access to the toolsets and precursors they need, even if they aren’t sure thus far what structure to b ...
Applications-based assessment for the printable electronics market
Printable electronics has been on an exponential growth curve for many years. Current prospects for printable electronics include sophisticated patterning to create memories and transistors; the varie ...
Image sensors adopt wafer-level packaging for mobile phone cameras
This month, SST presents a preview of the July edition of Chip Forensics, an online column by Dick James, senior technology adviser at Chipworks, a specialty reverse-engineering company that takes apa ...
Reduced capex: The new power play
The semiconductor industry has matured by most measures. With one exception, it is profitable, and managers appear to have figured out how to balance supply (capacity) with demand.
BUSINESS TRENDS
Global semiconductor sales are seen growing just under 5% in 2008, better than the 3.2% seen in 2007 but only half of the 9.1% expected just six months ago, according to new calculations from World Se ...
SEMATECH Litho Forum: Steady progress on all fronts
With almost all major R&D lithography efforts reporting at SEMATECH’s Litho Forum (May 12-14, 2008, Bolton Landing, Lake George, NY), the common theme resonating throughout a debrief with fo ...
Edge: the final cleaning frontier
Primarily driven by immersion lithography, defects on the wafer edge can transfer to the circuit areas and kill yield, and may be removed using wet etches, dry plasma etches, lasers, and mechanical ab ...
ALD comes to single-metal high-k gate stacks
Though semiconductor researchers spent years trying to identify an alternative to SiO2 for the transistor gate dielectric, it turns out that search was the easy part.
Novellus tips strip clean tools for logic, memory
Novellus Systems has released two new variations on its Gamma multi-station sequential processing (MSSP) architecture, targeting high volume memory and logic/foundry fabs.
New tool takes on flicker noise
Cascade Microtech has unveiled a new test system designed to measure flicker noise in ICs, seen as a barrier to lowering device operating voltages as geometries shrink–and a strategic initiative ...
Featured Products
The Imprio HD 2200 is the latest addition to the company’s family of Step and Flash Imprint Lithography (S-FIL) tools for hard-disk-drive (HDD) applications.
Product news
The Electro Plus Fusion Machine, with hand-held user interface, speeds the electrofusion joining process of thermoplastic pipe and fittings and can be used with several of the company’s piping s ...
Managing across-wafer process variation
Step-and-scan and resolution enhancements in optical lithography have enabled printing much smaller usable features.
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