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Solid State Technology

Volume: 51
Issue: 4
Date: April 01, 2008
Coating and deposition for flexible organic electronics
Developers of flexible, printed, and organic electronics (FPOE) products face significant challenges in scaling to true volume production.
Using scanner systematic signatures to enhance OPC modeling
At previous technology nodes, scanner systematic signatures–including illuminator pupil-fill and polarization, lens aberration, lens apodization, and flare–could be ignored without signifi ...
OPC model separability speeds computational lithography
In low k1 lithography, process integration and qualification are of little value without OPC-corrected masks.
Full-wafer post-via wet clean nonvisual defect inspection
The optimization of wet clean and surface preparation processes is an industry challenge, due in part to the lack of adequate inspection techniques to detect nonvisual defects (NVD).
Compensation for local proximity effects
Short range proximity effects in maskmaking processes require compensation over and above that presently applied to account for other effects such as electron backscattering.
On-the-fly threshold voltage measurement for BTI characterization
Advances in traditional CMOS scaling techniques are reaching their limits, bringing up the need for new materials and novel device designs.
Using existing production tools for low-cost thin wafer handling
In 2003, NXP CAEN opened a new pilot line dedicated to innovative solutions in system-in-a-package (SIP) on 150mm wafers.
Imprint litho forms arrays for new fault-tolerant nanoscale circuits
Extending Moore’s Law to 22nm and beyond for logic circuits calls for new concepts in manufacturing processes and device architectures.
Hermans leads accelerated MEMS development at IMEC
There’s much more going on at the Belgian research center IMEC than the relentless pursuit of Moore’s Law and semiconductor process technology scaling.
Technology News
It’s springtime for creative engineers
It’s springtime for engineers in electronics, computing, and chip architecture.
BUSINESS TRENDS
Worldwide semiconductor capacity and output both slowed significantly in 4Q07, but for the first time in a year and a half factory utilization rates crept up above the benchmark 90% level.
Featured Product
The Tachyon 2.5 computational lithography platform and the Tachyon DPT, an advanced double patterning technology (DPT) solution, have been introduced.
Product News
System improvements to the model 9200 PanelPrinter system include handling as many as 60 reticles on its automated reticle library subsystem, with automatic loading of up to 6 masks/layer.
Riding the wave of CMP
CMP is rapidly becoming one of the most important and widespread fab processes enabling the continuation of device shrinks.

Past Issues

2008

Volume Issue Date
51 11 Nov 01, 2008
51 10 Oct 01, 2008
51 9 Sep 01, 2008
51 8 Aug 01, 2008
51 7 Jul 01, 2008
51 6 Jun 01, 2008
51 5 May 01, 2008
51 4 Apr 01, 2008
51 3 Mar 01, 2008
51 2 Feb 01, 2008
51 1 Jan 01, 2008

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