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Solid State Technology

Volume: 49
Issue: 7
Date: July 01, 2006
Auto CD-SEM edge-placement error for OPC and process modeling
OPC models for leading-edge lithography must be calibrated with empirical data, and the measure of mismatch between design-intent and CD-SEM data is termed edge-placement error (EPE).
Searching for greater fab productivity with 300mm Prime
The ability to improve IC manufacturing costs has been one of the great success stories of the semiconductor industry.
Combining seed layers enables the use of HAR copper interconnects
The lower resistivity of copper vs. aluminum facilitates denser and faster ULSI devices with on-chip copper interconnects.
An alternative dopant-measurement method for analyzing ULE implant
This article describes an alternative dose-measurement method of analyzing ultra-low energy (ULE) ion implantation.
Evaluating topcoat options for immersion litho resists
Three resist systems are commonly available for 193nm immersion lithography: resist with solvent-soluble topcoat, resist with an aqueous developer-soluble topcoat, and special 193i immersion resist ne ...
Here comes the sun
Over the past 30 years, the solar industry has made a number of false starts, and the underlying photovoltaics (PV) technology has gained a reputation for being impractical without government subsidie ...
World News
Membership in the elite group of chipmakers spending at least $1 billion will expand to 16 companies this year, with memory firms particularly aggressive in their capacity investments, according to IC ...
“Bulking up” with direct silicon bonding
Layer-transfer technology is becoming more important as the demand for high-performance applications requiring enhanced semiconductor functions increases, and other applications such as MEMS and packa ...
The Open Modeling Coalition creates a new effective current source model
New models are needed to account for the process variations in nanometer-era silicon manufacturing, so that new chips can be designed with acceptable yield and performance without requiring costly re- ...
Containing wafer costs while customizing CMOS
In the late 1980s and early 1990s, CMOS became increasingly standardized as dimensions shrunk from 1µm to 0.
Targeting 45nm with improved SiON films and extended gate dielectrics
Silicon oxynitride gate-stack dielectrics are reaching limits for use beyond 65nm technology.
Optimizing gate dielectrics using laser-spike annealing
For the past several years, the need for advanced gate-stack materials has been listed by Sematech as one of the top technical challenges faced by the semiconductor industry [1].
Product News
The Cougar-SMT X-ray inspection system can image components in 2D and 3D for thorough inspection of applications requiring high magnifications, such as MEMS/MOEMS, semiconductor packages, and high-den ...

Past Issues

2006

Volume Issue Date
49 12 Dec 01, 2006
49 11 Nov 01, 2006
49 10 Oct 01, 2006
49 9 Sep 01, 2006
49 8 Aug 01, 2006
49 7 Jul 01, 2006
49 6 Jun 01, 2006
49 5 May 01, 2006
49 4 Apr 01, 2006
49 3 Mar 01, 2006
49 2 Feb 01, 2006
49 1 Jan 01, 2006

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