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Solid State Technology

Volume: 48
Issue: 7
Date: July 01, 2005
Improving yield at 65nm using Cu thickness monitoring and control
The dual-damascene process used to create copper interconnect exhibits nonuniformities in both Cu deposition and removal rates that, if not closely controlled, result in structures of varying thicknes ...
Organic growth on pattern side of reticles gives rise to new progressive mask defects
Unexplained progressive mask defects continue to plague and puzzle semiconductor manufacturers.
Removal of metal carbonyl and moisture impurities through POU purification of CO gas
An elaborate testing methodology is used to study the impurity removal characteristics of point-of-use carbon monoxide gas purifiers.
Meeting challenges for engineering the gate stack
Precise interfacial layer control and film compositional control are needed to extend SiON layers with high nitrogen content for 32nm node high-performance (HP) logic devices, as well as when Hf-based ...
S/D extension formation for sub-65nm transistors
The increasing demand for high-performance computers and the widespread use of more complex consumer products continue to fuel the scaling of leading-edge logic devices.
Options at the 45nm node include engineered substrates
Compatibility with existing design methodology dictates the continued use of planar transistors at the 45nm technology node.
Introduction of stress requires stress metrology methods
Although stress has been used to increase carrier mobility for the past several years, its measurement and control have also proven difficult.
Development to manufacturing using integrated scatterometry
Integrated scatterometry will be an essential part of the monitoring and control in product manufacturing at the 65nm node and beyond.
Data collection and networking capabilities enable pump predictive diagnostics
Predictive diagnostics techniques are applied to networked vacuum systems in wafer-processing applications using an array of data collection, mining, and advanced analysis concepts.
The urgent need for process collaboration
Makers of advanced microchips have been doing a magnificent job of bringing 300mm wafer fabs on stream and ramping to even better yields than they had hoped for as they moved from 130nm to 90nm.
World News
Technology News
Wafer manufacturing issues for III-V optoelectronics
Optoelectronic devices using III-V compound semiconductor materials are increasingly central to optical communications.
Chemistry and process challenges in advanced materials processing
The push of leading-edge manufacturing technologies toward sub-0.1μm feature sizes places extreme performance demands on manufacturing processes and equipment.
Fabrication and assembly of 3D MEMS devices
The ability to integrate mechanical elements with supporting electronics on a micro scale has bolstered microelectromechanical systems (MEMS) as an enabling technology, sparking interest in an impress ...
DFM issues new rules for IDMs, foundries
Solid State Technology asked industry execs to comment on the proliferation of DFM solutions and their integration into the product flow.
Semicon West 2005 Product Panorama

Past Issues

2005

Volume Issue Date
48 12 Dec 01, 2005
48 11 Nov 01, 2005
48 10 Oct 01, 2005
48 9 Sep 01, 2005
48 8 Aug 01, 2005
48 7 Jul 01, 2005
48 6 Jun 01, 2005
48 5 May 01, 2005
48 4 Apr 01, 2005
48 3 Mar 01, 2005
48 2 Feb 01, 2005
48 1 Jan 01, 2005

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