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Microlithography World

Volume: 17
Issue: 3
Date: August 01, 2008
Accelerating both sparse and dense OPC computation
Different layers of chips at and below 45nm have different optimal OPC strategies.
Extending lithography to the wafer’s edge
Edge bead removal processes must now tailor and inspect the edges of each layer of an immersion resist stack within the bevel at the very edge of the wafer to prevent catastrophic particle production ...
Measuring line edge roughness: Fluctuations in uncertainty
Line edge roughness (LER) is the deviation of a feature edge (as viewed top-down) from a smooth, ideal shape�that is, the edge deviations of a feature that occur on a dimensional scale smaller than ...
Automating the CD-SEM recipe process for 45nm technologies
An offline recipe creation process accelerates the monitoring of hotspots in volume manufacturing at the 45nm node.
Technology diversity
Scientific competition among companies has produced numerous solutions to the common problems of the semiconductor industry.

Past Issues

2008

Volume Issue Date
17 4 Nov 01, 2008
17 3 Aug 01, 2008
17 2 May 01, 2008
17 1 Feb 01, 2008

Previous Years

2007 2006 2005 2004 2003 2002 2000
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