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Solid State Technology - semiconductors, chips, integrated circuits
Latest News Technology Features Web Features Products
Steady progress reported on HK+MG for 32nm and beyond
Jan 07 -
Chipmakers are trying many paths toward high-k metal gate dielectric (HK+MG) CMOS for 32nm and beyond, and papers presented at IEDM 2008 in San Francisco, CA, showed steadily improving results even though the routes may vary. Still, getting to uniform manufacturable devices presents some tough challenges.
Taiwan DRAM bailout redux: Bailout numbers, who wants in, Elpida's role
Jan 06 -
Taiwan's National Development Fund reportedly is ready to appropriate about US $6B to underpin its DRAM and flat-panel display industries, but individual companies are still hashing out whether their individual needs will be met. And an outside party is stumping to be the island's DRAM consolidator to challenge Samsung.
SIA: Sales drop off a cliff in Nov.
Jan 05 -
Global semiconductor sales dropped precipitously in November, which though not unexpected adds an extra layer of anxiety as the industry analyzes consumers' holiday spending patterns and their influence over the early part of 2009.
Fab spending, capacity in 2009: The wild ride's not over yet
Jan 01 -
Spending on equipping of frontend semiconductor fabs is expected to plummet 31% in 2008 to $26 billion, and recent announcements suggest another 30%-40% decline in 2009, resulting in the lowest spending level over the past 10 years. This article tracks the changing landscape of semiconductor fab spending, and what the future holds for 2009 and beyond.
ASML “double-dips” with updated litho tool
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Double patterning immersion lithography will be the dominant manufacturing paradigm at 32nm, and ASML announced at SEMICON Japan (Dec. 3) a new exposure tool designed for the most litho-intensive version of it: LELE, or “double-dip.”
2009 Economic forecast Look for rebound by 2010
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During the first half of 2008, the chip market held up well, better in fact than many predicted, but come the second half, the repercussions of the US sub-prime disaster had spread to the bigger global financial system, tipping the US and Europe into recession.
Product News
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Dyneon’s Adona emulsifier eliminates the use of ammonium perfluorooctanoate (APFO)â??a salt derived from perfluorooctanoic acid (PFOA)â??from production of fluoropolymers, which the EPA has mandated to be eliminated in 2015.
A collaborative course for HDD manufacturing
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The hard disk drive (HDD) industry has been evaluating lithographically patterned media as a vehicle to maintain the ∼40% per year growth in areal density, to well beyond 1Tb/in2.
Featured Products
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The V6000 product line enables testing of both flash and DRAM memory on the same automated test equipment platform by changing to a new test program and probe card.
Fab spending, capacity in 2009: The wild ride's not over yet
Jan 01 -
Spending on equipping of frontend semiconductor fabs is expected to plummet 31% in 2008 to $26 billion, and recent announcements suggest another 30%-40% decline in 2009, resulting in the lowest spending level over the past 10 years. This article tracks the changing landscape of semiconductor fab spending, and what the future holds for 2009 and beyond.
Overlay control goes to high-order
Dec 24 -
More challenging overlay requirements are driving a trend to use high-order control knobs for production set-up of scanners. This article explores the overlay requirements that are driving this trend, the challenges involved with implementing in production, and the cost-of-ownership trade-offs between different high-order control strategies.
A measurement method for wafer-level 1/f noise
Dec 09 -
In MOSFETs used for analog and RF circuits, 1/f noise is an important figure of merit. This article describes a wafer-level measurement method and setup to evaluate the 1/f noise of MOSFETs, which can be automatically performed on the wafer and can measure <100Hz low-frequency noise components.
HP optimizes low-cost processing for inkjet printheads
Aug 22 -
One of the most common and most ignored types of chips is on almost every desk in this electronic world of ours -- the inkjet printhead. This edition of Chip Forensics examines a three-color printhead device out of Hewlett Packard's low-cost HP 60 Tricolor ink cartridge launched earlier this year.
Two different approaches to integrated MEMS
May 07 -
by Dick James, Senior Technology Advisor, Chipworks
May 12, 2008 - After the 45nm hype of the last few months, let's go to the other end of the CMOS scale and examine some interesting MEMS devices that are leading the penetration into new markets like consumer electronics -- and would not have been manufacturable without the deep etching processes that have evolved over the last few years.
SST September 2007: Looking inside Apple's iPhone: Rad-hard technology?
Sep 04 -
EXECUTIVE OVERVIEW In this edition of Chip Forensics, Dick James tears down Apple's 8GB iPhone, and the reverse engineering of a Peregrine RF switch similar to the one used by Apple within it, to look at the unusual silicon-on-sapphire (SoS) process used for its manufacture.
Quotes delayed at least 20 mins.
SPIE Advanced Lithography
February 22-27 2009
San Jose, CA
International Wafer-Level Packaging Conference
October 27-30 2009
Santa Clara, CA
The annual IWLPC explores cutting-edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.
Debra Vogler of Solid State Technology interviews Lars Liebmann, Distinguished Engineer, Design for Manufacturability at IBM, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Benjamin Eynon, Associate Director of Lithography, and Samsung assignee to SEMATECH, at the 2008 SPIE Advanced Lithography Conference. ; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Mireille Maenhoudt, Litho Process Development Group Manager at IMEC, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Franklin Kalk, CTO at Toppan Photomasks, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews John Sturtevant, RET Technology Support Manager at Mentor Graphics, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Christopher Sparkes, Sr. Director of Technology at Nikon Precision, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology;
White Papers Online Learning
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This interdisciplinary comprehensive tutorial will give a comprehensive overview of CMP fundamentals along with benefits, environmental and business perspectives, process integration and the latest developments in this rapidly growing field. The course is designed to give participants the understanding necessary to effectively develop or implement the CMP process
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