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Solid State Technology - semiconductors, chips, integrated circuits
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Semilab adds materials analysis to metrology scheme
Jun 30 -
Chris Moore, leader of Semilab's new USA division, talks to SST about the company's latest acquisition of materials analysis firm SDI, its assembled roster of metrology technologies, and a possible consequence of stalled 450mm discussions: equipment leasing.
28nm tapeouts proceeding according to plan
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Toppan Printing Co. Ltd. has established a new photomask manufacturing process at its photomask facility in Asaka, Japan, to support 32nm and 28nm semiconductor device production, through an ongoing joint development project with IBM.
Creating a data-driven tool architecture
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Data requirements for semiconductor manufacturing equipment have increased dramatically over the past decade. So much, in fact, that tool-control software purchased or built more than five years ago is probably already outdated.
Semiconductor Survivor Call for Entries
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These are difficult times for the semiconductor industry. Many would say the most difficult ever. Hopefully, we are nearing the end of the recession and prosperity will quickly return.
Memory sector ready to rebound? Not quite
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Signs that the DRAM market hit a bottom in 1Q and is poised to rebound don’t quite paint the whole picture, which from a broader perspective still shows things plodding along, far from a meaningful recovery.
The myth of infinite demand
Jun 24 -
The PV industry competes with many other energy options, some of which are less expensive, all of which are vying for a larger piece of the market. But the answer to unlimited demand for solar is not as simple as achieving grid parity -- it's the system price or cost that matters, and often this is overlooked.
EHS considerations in PV manufacturing equipment installations
Jun 17 -
A business risk management approach to PV equipment installation that incorporates environmental, health, and safety (EHS) considerations from the planning process through start-up can help reduce costs, minimize liability, and minimize timeframes.
ALD enables thin films for next-generation flash and NVM
Jun 08 -
In this article, ASM and Numonyx explain that ALD of high-k dielectrics and novel metal layers will be prevalent in producing next-generation NVMs, because it has been shown to address many of the issues related to speed, endurance, and reliability of these devices.
HP optimizes low-cost processing for inkjet printheads
Aug 22 -
One of the most common and most ignored types of chips is on almost every desk in this electronic world of ours -- the inkjet printhead. This edition of Chip Forensics examines a three-color printhead device out of Hewlett Packard's low-cost HP 60 Tricolor ink cartridge launched earlier this year.
Two different approaches to integrated MEMS
May 07 -
by Dick James, Senior Technology Advisor, Chipworks
May 12, 2008 - After the 45nm hype of the last few months, let's go to the other end of the CMOS scale and examine some interesting MEMS devices that are leading the penetration into new markets like consumer electronics -- and would not have been manufacturable without the deep etching processes that have evolved over the last few years.
SST September 2007: Looking inside Apple's iPhone: Rad-hard technology?
Sep 04 -
EXECUTIVE OVERVIEW In this edition of Chip Forensics, Dick James tears down Apple's 8GB iPhone, and the reverse engineering of a Peregrine RF switch similar to the one used by Apple within it, to look at the unusual silicon-on-sapphire (SoS) process used for its manufacture.
Quotes delayed at least 20 mins.
International Wafer-Level Packaging Conference
October 27-30 2009
Santa Clara, CA
The annual IWLPC explores cutting-edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.
Debra Vogler of Solid State Technology interviews Lars Liebmann, Distinguished Engineer, Design for Manufacturability at IBM, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Benjamin Eynon, Associate Director of Lithography, and Samsung assignee to SEMATECH, at the 2008 SPIE Advanced Lithography Conference. ; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Mireille Maenhoudt, Litho Process Development Group Manager at IMEC, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Franklin Kalk, CTO at Toppan Photomasks, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews John Sturtevant, RET Technology Support Manager at Mentor Graphics, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology; Debra Vogler of Solid State Technology interviews Christopher Sparkes, Sr. Director of Technology at Nikon Precision, at the 2008 SPIE Advanced Lithography Conference.; 193nm lithography; 22nm; CMOS manufacturing; Extreme Ultraviolet (EUV); Lithography; SST on the Scene at SPIE; double patterning; high-index immersion lithography; meeting overlay tolerances; nanoimprint lithography (NIL); solid state technology;
Original broadcast on March 27, 2009
Original broadcast on July 23, 2009
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Silicon Run Lite combines key sequences and images from both Silicon Run I and Silicon Run II. Live industrial footage, microscopic filming, animation, graphics and special effects give an up-close view of manufacturing.
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