Chris A. Mack, Austin, Texas

Moore’s Law, as practiced today by the semiconductor industry, is all about scaling. Feature sizes, overlay errors, operating voltages, drive currents–everything must scale in some fashion to enable the next generation of device technology. In lithography, as for semiconductor device manufacturing in general, the most basic unit of scaling is the minimum half-pitch on the device. Since the most important benefit of scaling is the ability to pack more transistors into a smaller area, the minimum half-pitch serves as the best (simple) measure of packing density, and thus overall scaling productivity.

But not everything scales at the same rate. Some parameters (such as voltage) scale more slowly, while others (such as photomask dimensional uniformity) scale more quickly. In this article, I’ll look at a few mask manufacturing specifications and show how and why those specifications are scaling at a significantly faster rate than the minimum half-pitch of the device.

In late 2007, the 8th edition of the International Technology Roadmap for Semiconductors (ITRS) was completed. The first “official” roadmap, the SIA’s Semiconductor Technology Workshop Conclusions, was published in 1993 based on a workshop held in Irving, TX, in November 1992; the document wasn’t called a “roadmap” until its second edition, in 1994. The stated goal of the workshop was to “?create a common vision of the course of semiconductor technology over the next 15 years.” Since 1997, this roadmap has been updated every two years. While each edition of the roadmap serves to predict the pace of the industry for the coming 15 years, the collection of these eight roadmaps also serves to show the actual pace that the industry has taken, since each roadmap begins with a snapshot of the industry status.

For example, the Table shows mask data extracted from the last seven roadmaps. For any given roadmap edition, the roadmap data from the report always begin with the roadmap year, and then make projections into the future. In the Table, I ignore the projections made in the roadmap reports, and simply extracted the current year’s data (i.e., the 2001 data comes from the 2001 edition of the Roadmap). Thus, we have a simple method for capturing lithographic trends over the last 10 years.

The Figure shows the relative scaling rates of several mask specifications over the last 10 years. Minimum half-pitch has shrunk by a factor of 4 over that time period, while gate CDs have shrunk somewhat faster (almost a factor of 5). Thanks to OPC, however, the minimum (primary) feature size on the mask has shrunk faster still–more than a factor of 6 in the last 10 years. But it is the critical dimension uniformity (CDU) specification for the mask that has scaled the fastest. Contact hole CDU specs have shrunk by a factor of 14 in the last 10 years, or more than 3× faster than the rate at which the minimum half-pitch has scaled. While everything in lithography becomes harder over time, mask-makers have earned more than their share of difficulties.

What happened to cause mask specifications to shrink significantly faster than wafer dimensions? There are three main reasons. In 2000, the industry discovered the mask error enhancement factor (MEEF), where a given percent change in mask CD results in a much higher percent change in wafer CD. As a result, mask CDU specifications shrank by a factor of 2?3 to compensate for MEEF (contact hole MEEF being the highest). By 2002, aggressive RET/OPC caused mask primary features to shrink faster than wafer dimensions. By 2004, double exposure processes put a bigger burden on mask image placement.

How will these mask specification trends play out in the near future? MEEF is getting higher, so that we can expect mask CDU specs to continue to shrink significantly faster than wafer CD. Also, it is likely that some form of double patterning will become mainstream in the next few years. Depending on the flavor adopted, we could see a significant tightening of mask image placement specifications beyond the normal scaling (by up to a factor of 3). Masks have gotten much harder to make in the last 10 years, even relative to the difficulties in wafer lithography. More of the same is in store for at least the next five years.

Chris A. Mack writes and consults on the field of semiconductor microlithography. He can be reached at 1605 Watchhill Rd., Austin, TX 78703; e-mail chris@Lithoguru.com.