Henning Haffner, Infineon Technologies NA Corp., Hopewell Junction, New York
Jason Meiring, IBM Systems and Technology Group, Hopewell Junction, New York
Zachary Baum, Scott Halle, Scott Mansfield, IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, Hopewell Junction, New York

Double patterning can shrink tip-to-tip spacings and improve across-chip and across-device linewidth variation (ACLV and ADLV) versus single exposure processes. A decomposition approach for gate levels using line-end extensions and printing assist features (PrAFs), with automatically generated cut shapes, is demonstrated.

Double patterning has quickly become the leading approach for printing the 32nm half-pitch (32hp) node with water immersion lithography because it can enable effective k₁ factors below 0.25. However, double patterning also has the potential to significantly improve processes with much higher k₁ factors by separately targeting two disparate feature types (e.g., dense and isolated lines) whose printing cannot be simultaneously optimized with a single exposure. This situation has become increasingly common as increases in NA, and the inherent loss in isolated-feature depth of focus (DOF), cause traditional strategies (e.g., subresolution assist features or SRAFs) to fall short. Because transistor performance is directly tied to linewidth control, gate level processes can benefit strongly from this type of double patterning.

The focus of this article is on enabling double patterning for random logic layouts, for which the decomposition process (i.e., the automatic splitting of a layout as drawn into two photomasks) is very challenging. Two techniques are employed: First, similar to other double patterning proposals for SRAMs [1, 2], line-ends are extended and then cut with a second exposure to achieve the tight tip-to-tip spacing requirements. Second, a pitch filling and cutting approach is used to meet the stringent through-pitch linewidth control specifications of logic gates. In the latter scheme, extraneous structures known as PrAFs are nested alongside isolated gates to make the gates appear dense (similar to SRAFs) [3, 4]. The PrAFs are then removed with the second cut exposure.

Double patterning process

Our double patterning process, more precisely called double exposure/double etch, or DEDE, is depicted in Fig. 1. In the first patterning step, gate features and the supporting PrAFs and line-end extensions are exposed and etched into an intermediate hard mask layer. (PrAFs are shown as the shaded resist features in the figure). In the second patterning step, resist trenches are opened over the features to be removed. After etch, the remaining hardmask is used to transfer the final desired pattern into the underlying patterning layer. By using this approach, the first exposure can be tuned for printing dense lines, and the second exposure can be optimized for isolated spaces.

Printing vs. subresolution assist features

It is worthwhile to illustrate how a process can benefit from the use of PrAFs as opposed to SRAFs. The focus of this analysis is on across-chip linewidth variation (ACLV), which is an important metric of overall linewidth control for gate level processes. While experimental ACLV measurements take all process variations into account, the simulations could only consider focus, dose, and mask variations. For each component, a normal distribution was assumed with a standard deviation denoted as σ. Resist CDs were calculated for all permutations of -3σ, 0σ, and +3σ, a total of 27 simulations. To obtain the correct probability when multiple terms were varied, a weighting factor was employed. From these simulations, the total 3σ ACLV was determined along with the individual contributions of focus, dose, and mask error to CD variation. This analysis was performed on 1D features across a large pitch range to compare the through-pitch performance of processes using optimized SRAF and PrAF schemes.

To develop the optimized PrAF process, an existing SRAF process was used as a starting point. Although SRAFs can be used in conjunction with PrAFs (for example, in semi-dense pitches where a PrAF wouldn’t fit), the dose and illumination conditions were changed such that assists were not required for the range of pitches that were too tight to place PrAFs. PrAFs were placed in a style that was essentially equivalent to SRAF placement. For the purposes of this study, the widths of the PrAFs were set equal to the main feature width.

For the initial screening of the different PrAF options, only biasing and DOF calculations were performed. If a given PrAF scheme exhibited good DOF, then the ACLV calculations were also conducted. Several candidate spacings (main-to-assist and assist-to-assist) were simulated through-pitch. The results indicated that adding PrAFs improved ACLV for pitches greater than about twice the minimum, with more PrAFs being better for the largest pitches.

A comparison between the original SRAF process and the new PrAF process is shown in Fig. 2. The results are somewhat mixed for a PrAF-only solution: While the PrAF process shows a clear ACLV advantage (up to 44%) in the intermediate pitch range, the SRAF process (because of lower MEEF) displays lower ACLV (by 18%) at the largest pitches. The optimal solution, therefore, is a combination of PrAFs and SRAFs, with SRAFs being used for largest pitches, where they show an ACLV advantage.

From these results, it is clear that an optimal assist feature strategy is highly dependent on the dose, focus, and mask variation factors. While PrAFs can significantly improve process performance, the impact of both PrAF and SRAF placement on CD variation must be assessed in this 3D space. While the lithographer should always seek to reduce process variations, an optimal assist strategy will help ensure the robustness of the process.

Mask layout generation

In the first stage of the decomposition process, all critical line-ends get extended by a certain minimum amount that can be determined by classic ground rule calculation approaches. First, this calculation needs to consider the CD tolerances of the gate level line-ends and the active area level underneath, and second, the process overlay tolerances between gate and active area as well as the gate level line-end shortening assumptions. Under the assumption that line-end extensions and/or PrAFs are allowed to connect to noncritical polyconductor lines, a significant decrease in the “poly gate line-end past active area” design rule can be realized. Compared to the rule for single-exposure processes, the value may be decreased by at least half. This translates into a significant area gain especially for designs using area-optimized logic cell libraries, with line-ends often being placed in dense environments.

Line-end extensions also have the result of moving any potential process-induced necking (or bulging) regions outside the active device area. The necking phenomenon is difficult to completely eliminate, even with optimized OPC, and is due to the more pronounced interference effects seen with aggressive illumination conditions. Without the extensions, the necking region occurs inside the device region and causes performance degradation. A potentially significant improvement in across-device linewidth variation (ADLV) and device performance can thus be realized.

In the next stage of decomposition, electronic design automation software is used to automatically add PrAFs to the originally drawn design layout. The PrAF placement and dimensioning is based on a rules-based, 1D table-a prerequisite for automated PrAF insertion into a 2D product design layout. This initial step must be followed by a comprehensive cleanup code that embodies the major part of the placement code innovation. The cleanup code itself is mostly driven by conflicts injected by input pitch differences of adjoining PrAFs as well as complicated 2D layout environments (Fig. 3).

The decomposition of the PrAF enhanced layout (Fig. 4b) into two mask levels is, from the automation point of view, much less complex than the PrAF placement and cleanup. As a general rule, all newly generated features on the polyconductor mask must be covered by a cut mask shape to ensure their removal in the second step of the double patterning process. To accomplish a clean removal, edges of the shapes on the final cut mask layout need to overlap the boundaries of the polyconductor shapes underneath except where line-ends are cut (Fig. 4c).

Thus prepared, the two mask levels can now be treated by OPC. One benefit of this method of double patterning is that no interlevel interaction needs to be considered, keeping the OPC as simple as it could get with the stringent tolerance requirements the gate level faces at and beyond the 45nm logic technology node.

Maskmaking also avoids significant requirements specific to double patterning. By construction, this technique is almost insensitive to overlay, neglecting some minor interactions that can be easily absorbed by ground rule definitions and the edge placement of the final cut mask layout, without jeopardizing the projected benefits.

Results

Predictive lithographic modeling was used in an attempt to go beyond 1D evaluations by using automated PrAF generation code applied to a realistic logic library cell layout. Image contours were simulated for various process conditions, and CD tolerance data were collected for the center and both “ends” of each gate where polyconductor lines cross active area edges.

The simulations considered a water immersion process using Quasar illumination with a 30° opening, inner/outer σ of 0.60/0.80, numerical aperture of 1.35, and a dose such that a 60nm line on the mask (1×) at 130nm pitch prints 50nm in width. The total gate count of the logic library cell layout was 176. The gates differed in their width, their individual embedding into a dense (on 130nm pitch), semi-isolated or one-sided isolated proximity environment, and their line-end area overlap with and past the active regions. All gates had the same 50nm target CD. The chosen approach furnishes not only an insight into ACLV but also into ADLV.

For the sake of simplification, the process and layout details were applied to a single exposure SRAF process and a double patterning PrAF process without any detailed optimization for either of the two RET schemes. Thus the illumination condition, dose anchoring, and PrAF and SRAF placement and dimensioning–as well as differences in minimum design rules driven by the two different RETs–were left “as is” for comparison purposes. The results shown here are only illustrative and would be subject to further optimization and more elaborate analysis to achieve production worthiness.

Figure 5 presents a histogram of gate CD data at nominal
and -50nm defocus, keeping all other process parameters constant. Since the double patterning PrAF process offers more assist feature flexibility, the single exposure SRAF process was expected to have more defocus-driven process variation.

The PrAF process shows an unchanged standard deviation of 2nm, accompanied by a mean shift of 2.3nm for nominal versus defocus. This supports the hypothesis of PrAFs minimizing the through-focus CD variation. On the other hand, there is still improvement potential by centering better at the iso-focal condition as well as improving OPC convergence at nominal. The standard deviation of the SRAF process increases through focus from 2.8nm at nominal to 3.4nm at -50nm defocus. The already-higher CD error at nominal can mostly be attributed to corner rounding effects at line-ends of polyconductors. As with the PrAF process, the CD variation at the nominal condition needs to be improved by optimizing the OPC. Overall, this makes the PrAF process’ CD tolerance at nominal being improved by 27% versus the SRAF process. At -50nm defocus, the improvement increases to more than 40%.

Figure 6 depicts a 45nm logic layout with critical lines at 180nm pitch. The upper row shows the original polyconductor and active area layout and its decomposition into two mask levels. The bottom row shows SEM images of the same layout using single exposure (left) and double patterning (right) processes. The rectangular line-end corners and the jaggedness of the resist contours are proof of the double patterning process as seen in the SEM image on the right of the bottom row.

Conclusion

Due to the inherent cost disadvantage of double patterning, it becomes crucial to gain more than just a minimized SRAM tip-to-tip spacing. The most important advantages made possible by the added enhancement features and their subsequent removal are:

• Corner-rounding-free line-ends everywhere, enabling the design rule for “polygate line-ends past active” area to be greatly reduced, thus realizing real estate savings; and
• ACLV and ADLV improvements due to increased regularity and uniformity of the polyconductor patterning process being always dense like a single contacted pitch.

However, simulations also show that it will be of utmost importance to ensure optimum performance with regard to CD tolerances for the most critical single contacted pitch, even for a 1D layout configuration, taking into account all major CD tolerance contributors such as focus, dose, and mask CD variations.

Acknowledgments

The authors wish to acknowledge contributions by Suniti Kanodia, Santo Credendino, Carlos Fonseca, and Haoren Zhuang. Additionally, the authors would like to thank Dario Gil, Tim Farrell, and Paul Schröder for providing management support and resources for this project.

This work has been supported by the independent alliance programs for SOI and bulk CMOS technology development projects at the IBM Microelectronics Div., Semiconductor Research and Development Center, Hopewell Junction, NY 12533 USA.

References

1. Yan Borodovsky, “Marching to the Beat of Moore’s Law,” Proc. SPIE, Vol. 6153 (SPIE, Bellingham, WA, 2006) 615301.
2. H. Zhuang, H. Wang, C. Yap, A. Gutmann, J. Lian, C. Sarma et al., “Patterning Strategies for Gate-Level Tip-tip Distance Reduction in SRAM cells for 45nm and Beyond,” Semiconductor Technology, ISTC 2007, Proc. Vol. 2007-01, 154-159, 2007.
3. J. Meiring, H. Haffner, C. Fonseca, S. Halle, S. Mansfield: “ACLV Driven Double-Patterning Decomposition With Extensively Added Printing Assist Features (PrAFs),” Proc. SPIE, Vol. 6520 (SPIE, Bellingham, WA, 2007) 65201U.
4. H. Haffner, J. Meiring, Z. Baum, S. Halle, ”Paving the Way to a Full-chip Gate-level Double Patterning Application.” Proc. SPIE, Vol. 6730 (SPIE, Bellingham, WA, 2007) 67302C.

Henning Haffner received his MS in electrical precision engineering from the Technical U. of Chemnitz in 1992. He joined Siemens/Infineon and its DRAM development alliance with IBM in East Fishkill, NY, in 1997, developing CAD solutions for RET and in particular, pioneering the process introduction of OPC. He works now as a senior staff engineer at Infineon Technologies NA Corp., 1983 Route 52, Suite 1, Hopewell Junction, NY 12533; ph 845/894-3069, e-mail Henning.Haffner@infineon.com.

Jason Meiring received his BS in microelectronic engineering from the Rochester Institute of Technology in 2000. He completed his PhD in chemical engineering in 2005 at the U. of Texas at Austin. In 2006, he joined the computational lithography group at IBM.

Zachary Baum graduated in 1986 from SUNY U. at Binghamton, NY, with a BA in mathematics and computer science. He joined IBM EDA, Microelectronics Division, in 1996, as a software consultant. In 2000, he joined the IBM Systems and Technology Group and has since been working in the area of computational lithography.

Scott Halle received his BA from Wesleyan U., his MS in electrical engineering from Columbia U., and his PhD in physical chemistry from the Massachusetts Institute of Technology (1990). After a postdoctoral fellowship in the department of physics at the U. of Tokyo, he began working at the Semiconductor Research and Development Center at IBM.

Scott Mansfield received his PhD in applied physics from Stanford U. in 1992 and his BS in applied and engineering physics from Cornell U. in 1987. He joined IBM in 1992 and has been developing RETs since 1996.