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Solid State Technology - semiconductors, chips, integrated circuits
SIA lowers chip growth forecast, but industry resilient against macro challenges
Jun 11 -- by James Montgomery, News Editor, Solid State Technology
June 11, 2008 - In its midyear forecast update/Webcast, the SIA has lowered its growth expectations for worldwide semiconductor sales to 4.3% (almost half the 7.7% it said six months ago), but SIA president George Scalise said the industry is actually doing quite well outside of the memory segment and is still showing immunity to broader US macroeconomic concerns....
Analysts parse industry strengths, challenges, opportunities at SEMI breakfast
Jun 09 -- by James Montgomery, News Editor, Solid State Technology
June 9, 2008 - A trio of semiconductor industry analysts presented their newest industry/macroeconomic analysis at a SEMI breakfast panel near Boston (June 4), generally agreeing that the IC industry isn't doing as badly as had been feared. Other topics addressed included capex trends and a coming "memory meltdown," concerns about long-term fab-lite models, IC makers vs. systems OEMs, and advice to suppliers about 450mm....
IITC panel: Moore's Wall still elusive
Jun 03 -- June 3, 2008 - Chris Malachowsky, co-founder, fellow, and SVP of operations of NVidia, gave a great perspective on the motivation for continuing the classic Moore's Law scaling trend for logic in an IITC evening panel discussion sponsored by Applied Materials....
Startups hit the fast track at UK event
May 23 -- by Françoise von Trapp, managing editor, Advanced Packaging
May 23, 2008 - Five silicon startups were introduced at the recent Born Global! event in Bath, UK, part of a program that aims to help startups clear an early strategic hurdle that can inhibit their interaction with potential customers and partners. Two of this year's participants, Robert Beat (Silicon Basis) and Nick Weiner (Xintronix), talked to SST about the FASTtrack program and their companies' goals....
Dan Hutcheson's "open mike" on 450mm
May 22 -- By Pete Singer, Editor-in-Chief, Solid State Technology
May 22, 2008 - Dan Hutcheson, president of VLSI Research, gave a wide-ranging talk on the economics of the 450mm wafer transition at The ConFab on Wednesday. Among the touchpoints: lessons learned from the "mishandling" of the 300mm transition, why equipment suppliers are reluctant to support it, why it's nearly impossible to predict the ROI of 450mm -- and what he thinks is a viable model for 450mm development....
SEMI: Suppliers see no net benefit in 450mm
May 22 -- by Pete Singer, Editor-in-Chief, Solid State Technology
May 22, 2008 - For a 450mm wafer-size transition to happen, suppliers need to be convinced that their initial investments will translate into sales and won't eat into their 300mm business. But speaking at the Confab, SEMI standards VP John Ellis indicated that suppliers still think there's no benefit to them -- and he presented new data showing that the cost modeling is flawed, and that investments are better used elsewhere....
450mm odds & ends: 450mm trumps "School Prime," questioning TSMC's 450mm push
May 22 -- by SST editors Bob Haavind, Pete Singer, Debra Vogler
May 22, 2008 - Tidbits gleaned from conversations and presentations about the 450mm debate: Reflections on AMD's "200mm Prime" efforts, and why 300mm-Prime tools are "silly;" how ROI -- and shareholders -- influence 450mm tool development; and why Japanese companies are headscratching at TSMC's public support of 450mm....
Progress amid the battle: ISMI's 450mm status report
May 22 -- by Debra Vogler, senior technical editor, Solid State Technology
May 22, 2008 - In the final ConFab 2008 session, amid the verbal volleying about whether 450mm manufacturing is needed and how would it be financed, ISMI's associate director Joe Draina reported on the progress being made in a number of areas, including the silicon wafer readiness project, wafer manufacturing infrastructure readiness, and a 450mm factory integration testbed....
True 3D needs EDA and 300mm
May 21 -- by Ed Korczynski, Senior Technical Editor, Solid State Technology
May 21, 2008 - In a session discussing the economic implications of 3D ICs, Qualcomm VP Tom Gregorich noted that 3D and through-silicon vias promise better performance and potentially greater freedom for chipmakers to customize functionality -- but warned that cost of integration remains an issue, and the technology still has challenges to overcome....
IDM economics at 32nm and beyond
May 21 -- by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - Masaaki Kinugawa, GM of Toshiba's Oita operations, discussed the tough challenges faced by fabs developing advanced processes today in his Confab talk, including increasing complexity of process and device technologies (and proportionally rising costs) -- and an ugly truth waiting around the corner at the 32nm node....
Samsung happy to be "fab-heavy"
May 21 -- by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - Byung-Hoon "Ben" Suh, VP of ASIC/foundry business development, Samsung Semiconductor, explained how his company has risen to be one of the top of the fab world through bold investment. As other IDMs choose to go "fab-lite" Samsung plans to make their chips and take their money by going "fab-heavy."...
Litho will get much tougher with double patterning, extensive computation
May 21 -- by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - There's a tough road ahead for lithography, with double patterning and complex computation as well as requirements for more litho-friendly design, explained ASML's Martin van den Brink, EVP of marketing & technology, speaking at the Next Generation Lithography session at The ConFab....
Redefining fab productivity from a waste perspective
May 20 -- by Pete Singer, Editor-in-Chief, Solid State Technology
May 20, 2008 - Taking a page out of the Toyota playbook, AMAT CTO/CMO Iddo Hadar challenged the audience at his Confab presentation to focus not on improving productivity but eliminating waste, including what he called "redistributed" waste across many semiconductor processes....
Fab facility design: When a slowdown is good
May 20 -- by Debra Vogler, senior technical editor, Solid State Technology
May 20, 2008 - Among the fab design trends noted by ConFab presenter Rick Whitney, COO of US operations at M+W Zander: The rapid rise in the cost of advanced processing equipment has outpaced the cost of building fabs in the last few years, though increasing facility costs are now in line with the consumer price index. And advances in cleanliness and footprints are allowing fab design rules to be a bit less stringent....
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