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Solid State Technology - semiconductors, chips, integrated circuits
ASML “double-dips” with updated litho tool
Jan 01 -- Double patterning immersion lithography will be the dominant manufacturing paradigm at 32nm, and ASML announced at SEMICON Japan (Dec. 3) a new exposure tool designed for the most litho-intensive version of it: LELE, or “double-dip.”...
Applied accelerating TSV implementation, launches Silvia etch tool
Jan 01 -- Sizing up a TSV market beyond the early adoptersâ??e.g., image sensors, server DRAM, and communication/mobile Internet devicesâ??Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation with a target cost <$150/wafer....
Haze and sun for mask symposium
Dec 01 -- Ever since lithographers began exposing with 193nm DUV light, photomasks have accumulated photochemical haze that eventually congeals into crystalline defects....
Diskcon: HDD litho crossover happening now
Nov 01 -- A full-day symposium at this year’s Diskcon USA (Sept. 14-18) explored the lithography implications of sub-ITRS roadmap feature sizes on disk drives, with the challenge that HDD lithography must cost 10Ã? less than NAND flash lithography, the lowest-cost semiconductor process....
MoSi-ing along to 32nm
Oct 01 -- The chrome material that has blocked the light on binary masks for a generation may finally have outlived its usefulness, according to Franklin Kalk, CTO of Toppan Photomasks, in an exclusive interview with SST....
Seeking process windows for 32nm USJs using MSA
Sep 01 -- Susan Felch, principal member of the technical staff, frontend development at Spansion, summarized research she conducted while at Applied Materialsâ??and done with IMECâ??at the West Coast Junction Technology Group meeting, sponsored by the northern California chapter of the American Vacuum Society (AVS) and held in conjunction with this year’s SEMICON West....
Intel eyes scalable FBC technology for 15nm and beyond
Aug 01 -- Among the papers presented by Intel at the VLSI Symposium was one describing fabrication of the smallest reported floating body cell (FBC) planar devices, with functional devices measuring down to 30nm gate length (#9.4, “A Scaled Floating Body Cell Memory with High-k + Metal Gate on Thin-Silicon and Thin-BOX for 15nm Node and Beyond”)....
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