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Solid State Technology - semiconductors, chips, integrated circuits

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ASML “double-dips” with updated litho tool
Jan 01 -- Double patterning immersion lithography will be the dominant manufacturing paradigm at 32nm, and ASML announced at SEMICON Japan (Dec. 3) a new exposure tool designed for the most litho-intensive version of it: LELE, or “double-dip.”...
 
Latest 32nm CMOS, memory beyond flash, plus novel devices detailed at 2008 IEDM
Jan 01 -- New memory concepts and the latest 32nm CMOS with metal gates and high-k dielectrics were highlights of the 2008 International Electron Devices Meeting (IEDM) in San Francisco, Dec. 15-17....
 
Applied accelerating TSV implementation, launches Silvia etch tool
Jan 01 -- Sizing up a TSV market beyond the early adoptersâ??e.g., image sensors, server DRAM, and communication/mobile Internet devicesâ??Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation with a target cost <$150/wafer....
 
Haze and sun for mask symposium
Dec 01 -- Ever since lithographers began exposing with 193nm DUV light, photomasks have accumulated photochemical haze that eventually congeals into crystalline defects....
 
Inside Oxford/TDI’s HVPE technique for InGaN growth
Dec 01 -- TDI, an Oxford Instruments company, recently announced that it has developed a hydride vapor phase epitaxy (HVPE) technology that is based on a GaCl3-InCl3-NH3 system....
 
KLA-Tencor gets the noise out with latest plasma monitor
Dec 01 -- KLA-Tencor recently introduced the PlasmaVolt X2 for measurement of plasma chamber conditions in semiconductor wafer processing systems....
 
Diskcon: HDD litho crossover happening now
Nov 01 -- A full-day symposium at this year’s Diskcon USA (Sept. 14-18) explored the lithography implications of sub-ITRS roadmap feature sizes on disk drives, with the challenge that HDD lithography must cost 10Ã? less than NAND flash lithography, the lowest-cost semiconductor process....
 
Slurry reduction is “groovy” at Rohm and Haas
Nov 01 -- Rohm and Haas Electronic Materials recently announced CMP pad groove designs that enable defect and slurry reduction....
 
MoSi-ing along to 32nm
Oct 01 -- The chrome material that has blocked the light on binary masks for a generation may finally have outlived its usefulness, according to Franklin Kalk, CTO of Toppan Photomasks, in an exclusive interview with SST....
 
IMEC, ASML: Another step closer to production-worthy EUV
Sep 01 -- Kicking off this year’s SEMICON West, IMEC said it has been able to achieve electrically functional 32nm SRAM cells (FinFETs)....
 
Seeking process windows for 32nm USJs using MSA
Sep 01 -- Susan Felch, principal member of the technical staff, frontend development at Spansion, summarized research she conducted while at Applied Materialsâ??and done with IMECâ??at the West Coast Junction Technology Group meeting, sponsored by the northern California chapter of the American Vacuum Society (AVS) and held in conjunction with this year’s SEMICON West....
 
Dow Corning targets maskless lithography with latest e-beam photoresists
Aug 01 -- Dow Corning Electronics’ silicon lithography solutions group announced the commercial availability of Dow Corning XR-1541 e-beam resists, designed to enable the development of next-generation, direct-write lithography processing technology....
 
Intel eyes scalable FBC technology for 15nm and beyond
Aug 01 -- Among the papers presented by Intel at the VLSI Symposium was one describing fabrication of the smallest reported floating body cell (FBC) planar devices, with functional devices measuring down to 30nm gate length (#9.4, “A Scaled Floating Body Cell Memory with High-k + Metal Gate on Thin-Silicon and Thin-BOX for 15nm Node and Beyond”)....
 
Report from VLSI Symposium: Planar CMOS to 22nm, at most
Aug 01 -- This year’s VLSI Symposium meeting (June 16-19, Waikiki, HI) highlighted 45nm to 16nm CMOS technology....
 
 

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